Tagged memory is one of the most promising ways to achieve memory safety. The ARM architecture supports such technology since version 8.5 under the name memory tagging extension (MTE). In this work we explore a memory tagging approach for RISC-V CPUs using low latency ciphers. In particular, instead of storing the tag in RAM alongside the data, the tag is used to encrypt the data in RAM. This has the advantage that larger tags (providing higher levels of security) are possible and no extra RAM is needed to store tags.

What you'll learn:

• Working principles of hardware assisted memory safety, in particular tagged memory
• Properties of low latency ciphers
• How tagged memory can be enhanced using low latency ciphers